1. Field of the Invention
The present invention relates to a method for forming a patterned resist in manufacturing an integrated circuit, and, more particularly, to a method for forming a smaller patterned resist using silylation.
2. Description of the Background Art
An integrated circuit (IC) having a transistor, a resistor, a condenser or the like mounted on one chip has been recently used not only for information and communication appliances but also for many industrial appliances. The IC has helped every kind of industrial appliances to have a higher precision and intelligence. The IC has been developed to an LSI, a VLSI, and a ULSI as the integration density has been increased.
As to the IC, thousands of transistors were integrated on a several mm square chip around 1970. In these days, however, more than millions of transistors are integrated on a chip. Meanwhile, a width of an interconnection formed in an IC has been decreased from about 10 .mu.m to not more than 1 .mu.m.
Many advantages can be obtained by miniaturizing elements formed in an IC and increasing the integration density. As the size of an element becomes smaller, an IC can be more compact and lighter, and also the cost of manufacturing can be reduced. In addition, by uniting more elements, fewer connections made by soldering or the like are necessary, and therefore reliability of the IC improves.
Furthermore, if the length of an interconnection between elements is shorter because of an increased integration density, a time required for processing signals in an IC can be dramatically shortened, which results in reduction of power consumption. In case of a MOS integrated circuit, for example, under a scale down low, if dimension of an element is 1/k, a delay time is 1/k and power consumption is decreased to 1/k.sup.2 per element.
An increase of the number of elements in one chip for increasing an integration density of an IC depends on the technology of forming many fine structures on a wafer. In the technology, a process in which resist is applied onto a wafer and patterned to a desired shape is a key to the formation of very small structures. The process must be repeated ten and several times at most until a VLSI is finished.
For example, when a transistor is formed on a silicon substrate, a source portion and a drain portion are formed through the step shown in FIG. 1 using resist. Referring to FIG. 1, first, a silicon substrate 11 on which an oxide film 18 is formed is prepared (FIG. 1A). A photoresist film 12 is applied to oxide film 18 (FIG. 1B). A photomask 13 is provided above photoresist film 12 and ultraviolet rays 14 are directed to the photoresist film through photomask 13 (FIG. 1C). After developing and baking, a resist pattern 12' having a predetermined shape is obtained (FIG. 1D). Etching is then carried out, and only the portion of the oxide film which is not covered with resist pattern 12' is removed (FIG. 1E). After a resist pattern is removed by plasma ashing, impurities are diffused into an uncovered portion of a silicon substrate to form a source portion 19 and a drain portion 20 (FIG. 1F).
In order to form an interconnection on the substrate, for example, a step shown in FIG. 2 can be adapted. Referring to FIG. 2, first, an aluminum layer 30 is deposited on a substrate 21 (FIG. 2A). As shown in FIG. 2b, after a resist film 22 is formed on aluminum layer 30, ultraviolet rays 24 are directed to resist film 22 through photomask 23 (FIG. 2C). Development and baking are then carried out to obtain a resist pattern 22' (FIG. 2D). After only an uncovered aluminum layer is removed by etching and then a resist pattern is removed by plasma ashing, an interconnection layer 30' having a desired shape is obtained (FIG. 2E).
In the above described process, it is obvious that the size of elements to be formed and a width of an interconnection layer depend on the size of a resist pattern. In order to form a smaller element and a narrower interconnection layer, it is necessary to produce a finer patterned resist. Therefore, processing technology of a resist film is very important for increasing an integration density of an IC.
As one of the technologies for forming a finer resist pattern, there are methods of using silylation and dry development. One of the most well-known methods is a DESIRE system disclosed by Coopmans and Roland in 1986 (Proceeding of SPIE 631,34 (1986)). The basic steps of the system will be described with reference to FIG. 3.
As shown in FIG. 3A, first, a resist layer 32 is formed on a substrate 31. The resist layer can be formed of material available from UCB Electronics (Belgium) or Japan Synthetic Rubber Co., Ltd. under a product name of "PLASMASK". PLASMASK includes novolak resin and quinonediazide as main components. Novolak resin and quinonediazide are expressed by the following chemical formulas. ##STR1## After the material is applied to the substrate, for example, by a spinner, prebaking is carried out at an appropriate temperature.
Then, ultraviolet rays 34 of wavelength 248 nm-436 nm are directed to resist layer 32 covered with a mask 33 as shown in FIG. 3B.
After exposure, the substrate is placed within a vacuum chamber, and heated at about 120.degree.-200.degree. C. While an exposed region of the resist layer 35 is stable against heating, a crosslinking reaction proceeds by heating in unexposed region 37.
Thereafter, a hexamethyldisilazane (HMDS) gas is introduced into the vacuum chamber at an appropriate temperature by using N.sub.2 as a carrier gas and sprayed onto the substrate. HMDS is selectively received only by the exposed portion of the resist layer. In the exposed portion, for example, in blackened portion 36 shown in FIG. 3C, a silylating reaction occurs as shown by the following formula. ##STR2##
Following that, the resist layer is subjected to dry development using reactive ion etching (RIE). In RIE, O.sub.2 plasma is used. In the dry development, a silicon compound SiO.sub.2 is formed in the portion 36 where selective silylation has occurred (FIG. 3D). While the portions in which SiO.sub.2 is formed are resistant to RIE, the other portion in which no HMDS is received is formed only of material volatilized by oxidation, so that it is etched by RIE. The dry development results in a patterned resist having only the exposed region of the resist layer left as finally shown in FIG. 3E.
The DESIRE system is applied in order to form a fine resist pattern. However, in the system, a resist pattern whose side portion is etched by RIE tends to be formed. That is, as shown in FIG. 4, a resist pattern 40 having narrow parts tends to be formed because of side etch or under cut. When a finer resist pattern is formed, such a resist pattern having narrow parts may lean or collapse.
A method in which the side-etch can be prevented in RIE with a multi-layer resist film system is disclosed in Japanese Patent Laying-Open No. 2-24661. The method will be described with reference to the figures.
Referring to FIG. 5A, a first resist layer 52 is formed on a semiconductor substrate 51. A second resist layer 53 including silicon is deposited on first resist layer 52 (FIG. 5B). After a third resist layer 54 is formed on second resist layer 53 (FIG. 5C), third resist layer 54 is exposed using a mask having a predetermined pattern (FIG. 5D). The third resist layer is developed, so that resist pattern 54' is obtained (FIG. 5E). Using resist pattern 54' as a mask, second resist layer 53 is anisotropically etched (FIG. 5F). Using resist pattern 53' formed of the second resist layer as a mask, the first resist layer is anisotropically etched. This anisotropic etching is temporarily interrupted after about a half of first resist layer 52 is etched. At this time, resist patter 54' of the third layer is removed (FIG. 5G). Thereafter, as shown in FIG. 5H, silicon is introduced onto the surface 55 of first resist layer newly formed by etching, so that a silylated layer 56 is formed. A horizontal portion of silylated layer 56 is anisotropically etched away (FIG. 5I). Thereafter, first resist layer 52 is anisotropically etched again until semiconductor substrate 51 is uncovered. As a result, as shown in FIG. 5J, patterned resist 52' is obtained.
In this method, by forming a silylated layer on a side portion of a first resist layer, the first resist layer is protected and formation of a resist layer having narrow parts is prevented, as in the DESIRE described above. However, in this method, when a first resist layer is patterned, two additional resist layers must be formed. This increases the number of steps for forming a patterned resist. As described above, since a process for forming a resist pattern is repeated many times in manufacturing an LSI, the time and cost required for manufacturing an LSI increase as the number of steps necessary for one process increases.
In addition, in the above described method, a layer much thinner than a first resist layer must be deposited on the first resist layer to be patterned. Such a thin layer is susceptible to dust. If the layer is affected by dust and a resist pattern having a desired shaped can not be obtained, a yield in manufacturing an LSI decreases.
Furthermore, as shown in FIGS. 5H through 5I, if direction of the etching is not controlled well in the step of removing a horizontal portion of a silylated layer by anisotropic etching, there is a possibility that a silylated layer formed on a side surface is also etched away. Therefore, in this method, a possibility of etch back as described above remains.